Project. Work package 4: SpaceWire-RT VHDL IP core development

Objectives:

This work package will design and validate a VHDL IP Core for SpaceWire-RT aimed at FPGA implementation.

Work Package Leader:

UoD

Deliverables:

4.1 SpaceWire-RT Initial FPGA VHDL IP Core Validation Plan.

4.2 Revised SpaceWire-RT Outline Specification.